STARM · HW-09 · HARDWARE
Trojan Logic in FPGA
STARMCatalog entries from the DIPS Threat Inventory. The paper cites that dataset and does not use this name.
Malicious code embedded in FPGA bitstream.
Severity in the dataset9/10
Not the paper’s H/M/L.
- Target
- System Logic
- Layer in the inventory
- FPGA / Logic gates
- Mitigation
- Bitstream encryption and authentication.
- How the inventory says to fix it
- AI: Structural analysis of bitstream logic to identify hidden trigger-activation patterns.
- Quick fix
- Reload bitstream
- ML approaches named
- Random Forest (RF), XGBoost, Logistic Regression, and Support Vector Machines (SVM), Recurrent Neural Networks (RNN) and Long Short-Term Memory (LSTM)
- Methodology
- Detetcing malicious modifications to bitstreams or Register Transfer Level (RTL) code. Pattern detection and side-channel analysis
- Handler role
- FPGA Developer
- Stage
- Development
- Standard named
- IEEE 1735
- Status in the inventory
- Status unknown
STARMCatalog entries from the DIPS Threat Inventory. The paper cites that dataset and does not use this name.
Connection recorded in the inventory
Hardware Backdoors